1. Field of the Invention
The present invention relates to a method and an apparatus for leveling a semiconductor wafer by means of an etching treatment with locally different removal of material. The invention also relates to both a semiconductor wafer with improved flatness and nanotopography and to an SOI wafer with a homogenous layer thickness which are obtainable by the method.
2. Background Art
A semiconductor wafer, in particular a single-crystal silicon wafer for use in the semiconductor industry, has to have a high flatness, in particular in order to meet the requirements for the production of integrated circuits. A generally recognized rule of thumb states that the SFQRmax value of a semiconductor wafer must be no greater than the line width of the components which are to be produced on the semiconductor wafer. To allow the integration of the maximum possible number of circuits, the required flatness must moreover extend as close as possible to the edge of the front surface, the front surface being defined as the surface on which the components are to be produced. This means that the measurement of flatness must be carried out with only a very small edge exclusion, and the specified flatness values need to be satisfied not only by what are described as the full sites, but also by the partial sites. Full sites are surface elements on which complete components can be produced, whereas partial sites are surface elements at the edge of the wafer, on which there is insufficient space for complete components.
In defining the flatness of semiconductor wafers, the SEMI standard M1-94 draws a distinction between global flatness and local flatness. The global flatness relates to the entire wafer surface minus an edge exclusion which is to be defined. It is described by the GBIR (“Global Back Surface-Referenced Ideal Plane/Range”), which is a range of the positive and negative deviation from a back surface-referenced ideal plane for the entire front surface of the semiconductor wafer, which corresponds to the term TTV (“Total Thickness Variation”) which was previously customary. The local flatness relates to a limited area on the semiconductor wafer, which generally corresponds to the area of the component to be produced thereon. It is often expressed as the SFQR (“Site Front Surface Referenced Least Square/Range”), a range of the positive and negative deviation from a front surface, defined by error square minimization, for an area of defined dimensions. The variable SFQRmax represents the highest SFQR value for all the component areas on a defined semiconductor wafer. In the case of SFQR, it is always necessary to state the area to which the value given relates, for example an area of 26×8 mm2 in accordance with the ITRS Roadmap.
A further flatness parameter is what is known as the nanotopography. This is defined as the peak-to-valley deviation in a predetermined surface element, e.g. 2×2 mm2. The nanotopography is measured using measuring units such as ADE CR 83 SQM, ADE PhaseShift Nanomapper, or KLA Tencor SNT.
The flatness in the edge region of a semiconductor wafer is crucially influenced by what is known as the “edge roll off”. “A New Method for the Precise Measurement of Wafer Roll off of Silicon Polished Wafer”, Jpn. J. Appl. Phys. Vol. 38 (1999), 38-39 describes how to measure the “wafer roll off”, or edge roll off. Edge roll off can occur both on the front surface and on the back surface of the semiconductor wafer. It can have a crucial influence on the SFQR values of the area elements located at the edge of the wafer. An edge roll off is disruptive in particular in the case of semiconductor wafers which, for example to produce SOI wafers, are bonded to a further semiconductor wafer, since the edge roll off of the wafer surfaces which are to be bonded to one another has a considerable influence on the bonding quality at the edge of the wafer.
Currently, semiconductor wafers which are used as substrates for the production of microelectronic components are generally produced by the following conventional process sequence: sawing, lapping and/or grinding, wet-chemical etching, stock-removal polishing and mirror polishing. It has been found that this process sequence is unable to ensure the flatnesses required for the ever-decreasing line widths.
In EP 798 766 A1, a vapor-phase etching step using PACE (plasma assisted chemical etching) process followed by a heat treatment is inserted between stock-removal polishing and mirror polishing in the conventional process sequence, in order to improve the flatness of the semiconductor wafer. It is demonstrated on the basis of processing of silicon wafers with a diameter of 200 mm, that the process sequence described allows GBIR results of 0.2-0.3 μm. The document does not give any local flatness data. Furthermore, it does not state the size of the edge exclusion for the flatness measurement. EP 961 314 A1 describes a similar method. After sawing, grinding, PACE and mirror polishing, GBIR values of at best 0.14 μm and SFQRmax values of at best 0.07 μm are achieved.
The PACE process, as proposed in EP 961 314 A1, leads to a deterioration in the roughness of a polished wafer, which can be partially reduced by a hydrophobizing step immediately before PACE. PACE has to be carried out in vacuo, which makes the process complex in terms of the equipment required. Moreover, the semiconductor wafer is contaminated with the decomposition products of the gases used for etching, requiring an additional cleaning step, as described in EP 1 100 117 A2. Also, this process is not carried out over the entire surface, but rather by scanning the semiconductor wafer. This is, on the one hand, very time-consuming, and on the other hand, leads to problems with regard to the nanotopography in the scanning overlap region and to problems with regard to flatness (SFQRmax and edge roll off) in the outer region of the semiconductor wafer, up to a distance of approx. 5 mm from the edge of the wafer. One possible cause is the increased suction at the edge of the semiconductor wafer and therefore a reduction in the etching medium, since work is carried out in vacuo. The required overlap during scanning has an adverse effect in particular on the nanotopography at the overlap positions. The larger the diameter of the nozzle which is used to supply the etching medium, the worse the deterioration becomes. However, for economic reasons the nozzle diameter cannot be selected to be as small as may be desirable.
Consequently, the methods which are known in the prior art are unable to satisfy the geometry requirements for components with line widths of less than or equal to 65 nm, that is to say SFQRmax values of at most 65 nm. In this context, the most serious problems occur in the edge region of the semiconductor wafer, since the edge exclusion of currently 3 mm (for line widths of 90 nm) is reduced to 2 mm or 1 mm for the future line widths of 65 nm or less, and the partial sights are also taken into account when assessing the flatness.
An additional problem arises in the case of what are known as SOI wafers. These semiconductor wafers have a semiconductor layer which is located on a surface of a base wafer or handle wafer. The thickness of the semiconductor layer varies as a function of the components to be processed. In general, a distinction is drawn between what are known as “thin layers” (thickness less than 100 nm) and what are known as “thick layers” (from 100 nm to approx. 80 μm). The base wafer may either consist entirely of an electrically insulating material (e.g. glass, quartz, sapphire) or may, for example, consist of a semiconductor material, preferably silicon, and merely be separated from the semiconductor layer by an electrically insulating layer. The electrically insulating layer may, for example, consist of silicon oxide.
SOI wafers are very important for the production of microelectronic components. The semiconductor layer of an SOI wafer has to have a very homogenous thickness all the way into the outermost edge region. In particular in the case of semiconductor layers with a thickness of 100 nm or less, the transistor properties, for example the threshold voltage, vary very considerably in the case of inhomogeneous layer thicknesses. The absolute thickness tolerance for SOI wafers with thin and thick semiconductor layers depends on the layer thickness. The measurement method used to measure the layer thickness is preferably spectroscopic ellipsometry, reflectometry or interferometry.
To allow the integration of a maximum number of circuits, moreover, the required layer thickness homogeneity has to extend as close as possible to the edge of the front surface. This in turn means a very small edge exclusion.
U.S. Pat. No. 6,306,730 relates to a standard process for producing SOI wafers, in which hydrogen ions are implanted to a predetermined depth into a silicon donor wafer or top wafer, the implanted donor wafer is bonded to a base wafer and then the bonded wafers are separated along the layer of implanted hydrogen. By controlling the implantation depth, a layer thickness homogeneity (standard deviation from the mean layer thickness) of 0.47 nm for a layer thickness of 130 nm is achieved after separation. Immediately after separation, however, the surface of the silicon layer has a high roughness. Consequently, a chemical mechanical polishing (CMP) step has to be carried out after separation, and after any further steps for thinning the silicon layer. This chemical mechanical polishing step on the one hand reduces the roughness, but on the other hand also has a significant adverse effect on the layer thickness homogeneity, in particular at the edge of the wafer. U.S. Pat. No. 6,306,730 B2 does not disclose either the layer thickness homogeneity for the polished end product or an edge exclusion for the intermediate product following separation.
Methods for the aftertreatment of an SOI wafer with a view to improving layer thickness homogeneity are also known. These are generally local etching methods involving scanning the SOI wafer, with greater amounts of material being removed by etching at locations where the layer thickness is higher. In accordance with US 2004/0063329 A1, the surface of the SOI wafer is scanned in a dry etching process by a nozzle which is used to locally supply a gaseous etching medium. EP 488 642 A2 and EP 511 777 A1 describe methods in which the semiconductor layer of the SOI wafer is exposed to an etching medium over its entire surface. However, this etching medium has to be locally activated by a laser beam or a light beam from a light source focused using an optical system scanning the surface (photochemical etching).
All methods in which the surface of the semiconductor layer has to be scanned in order to achieve a locally different removal of material by etching are very time-consuming and therefore expensive. Moreover, the scanning requires a complex motion on the part of the light source or the nozzle, on the one hand, or the SOI wafer, on the other hand.
Moreover, additional inhomogeneities in the layer thickness occur in particular in the edge region of the wafer, i.e. in a region up to 5 mm from the edge of the wafer, and in the regions in which the overlap occurs during scanning. Given a layer thickness of 520 nm, according to EP 488 642 A2, a layer thickness homogeneity of 10 nm is achieved, without any details being given as to the edge exclusion. According to EP 511 777 A1, with a layer thickness of 108 nm, a layer thickness homogeneity of 8 nm is achieved, although again no edge exclusion is indicated.
Therefore, despite the complex methods, the required layer thickness homogeneities are not achieved, in particular in the edge region of the SOI wafer.